All microprocessors require some form of interface to off-chip memory and peripherals. There have been several different approaches taken in the prior art to achieve this. These are providing a simple generic interface, providing an interface to a specific memory device type and providing an adaptable memory interface.
Providing the microprocessor with a fairly simple generic interface has the advantage of being easy to design and uses relatively few device pins. This enables a low cost design of the microprocessor. Because the memory interface is not targeted at any particular memory or peripheral devices, almost any system using the microprocessor will require external hardware to customize the generic interface to the specific requirements of the memories used. This makes the system cost greater. Furthermore, it may be difficult to use the memory devices to their full potential using the external hardware.
Providing the microprocessor with an interface for a specific memory device is also simple to design and economical in device pins. It will result in a simple system design with minimal external hardware, but only if the system is constructed using the memory devices of the type for which the interface is constructed. For a microprocessor not targeted at a specific well defined set of applications, this limitation is probably too restrictive. Using the microprocessor with memories other than those for which the interface is targeted will require external system hardware as in the case of a generic interface. It may also be difficult to use the memory devices to their full potential. Furthermore, it becomes difficult to take advantage of improvements in memory technology over the lifetime of the microprocessor. It is possible to provide the same microprocessor core with differing memory interfaces, but this requires plural designs and stocking more than one highly similar part.
Using an adaptable interface a microprocessor can provide direct support for several different types of memory device. This allows a wide variety of applications to be supported without making any assumptions about how systems designers will want to use the microprocessor. The general principle behind an adaptable memory interface is that external hardware decodes the address output by the processor and returns information to the processor about the type of memory at that address location. The processor uses this information in order that the processor can access that memory appropriately. This is the approach taken by the Texas Instruments TMS320C80. The scheme currently employed is designed around DRAM-like memory cycles consisting of a row access and a number of column accesses. Every time a new row access is required, the external hardware must provide a new configuration via a number of input pins. The Texas Instruments TMS320C80 provides 13 input pins for external hardware to signal the new configuration. Although little external hardware is required between the processor and the memories, the extra input pins and the external decode logic required to control them both add extra cost to the system. Furthermore, the time required to decode the address output by the processor and set the input pins to the appropriate levels tends to reduce the overall bandwidth of the system.